For the first time the GCC source code mentions optimizations named "BDver4". This suggests that AMD are committed to their development plan for major architectures and will at least further develop it until Excavator. "BDver1" means "Bulldozer", which was first introduced in 2011; "BDver2" is "Piledriver". This architecture with slight improvements is the basis for current FX CPUs and the "Richland" APUs. "BDver3" is "Steamroller", which will introduced by AMD at the end of the year with "Kaveri" APUs.
The optimization hint at the fact that, with Excavator, AMD will support the Intel's AVX2 instruction set. AVX2 expands the 256-bit floating point operations by 256-bit integer operations. Nevertheless, AVX2 will be running on the FPU, which means that AMD will either have to considerably upgrade it, or even develop it from scratch. The current FPU only provides for a maximum of 128-bit integer operations used in the XOP instruction set. This could result in a substantial increase in performance of the FPU. There is not much more information on Excavator yet, only that Steamroller will feature a highly improved frontend with two decoders per module.