A quick look at our price comparison makes clear the majority of notebooks currently available is equipped with an Intel CPU. In the next few weeks the situation is set to change, at least according to AMD. AMD's new "Carrizo" APUs are supposed to change the status quo. "Carrizo" is the first APU to bring high-end technologies to mid-range devices, and it has made a big jump especially in terms of performance and energy efficiency compared to the previous generation.
The US chip manufacturer focused on streaming high-resolution videos, using office suites and online games. With "Carrizo", AMD is targeting the market for notebooks priced 400 and 700 US dollars. The mid-range market covers approximately 63 million potential customers, states AMD. Around 38 percent of notebook buyers will opt for a device between 400 and 700 US dollars. By the end of the year each second of fives devices sold will be in this price range.
While Intel's "Broadwell" CPUs for the notebook market have been made in the modern 14nm process, "Carrizo" continues to be made using 28nm technology. Nonetheless, AMD claims to have significantly improved the efficiency of its sixth generation APUs, compared to the previous "Llano", "Trinity", "Richland", "Kaveri" and "Beema" generations. "Carrizo" requires up to 40 percent less power, while perfomace was increased by about 25 percent. Although the number of transistors rose by around 29 percent to 3,1 billion, the chip continues to be sized 245 mm2.
The new "Excavator" cores were rearranged in line with the "High Density Library" layout, meaning the cores occupy 23 percent less surface on the die using the same manufacturing process, greatly increasing the packing density. AMD didn't leave the vacant space unused and integrated the entire Southbridge for the first time, which is why the company talks of the first true SoC. However, "Carrizo's" L1 cache now needs now more space, its capacity per core has increased from 16 to 32 KB, twice as much compared to "Steamroller". Thanks to further improvements lower latencies have also been achieved. The buffer size for the branch prediction has been increased by 50 percent from 512 to 768 entries. The L2 cache has however halved to 2MB, and there continues to be no L3 cache.
The increase in power efficiency is due to a revised power management. AMD here used its so-called Adaptive Voltage Operation. So far, the voltage was always a bit higher than necessary, in order to create stability because of unavoidable fluctuations. For "Carizzo" this is no longer the case. Instead, the average voltage is slightly reduced, and the core clock speed is slightly lowered in the event of larger fluctuations. However, AMD claims this won't have too much of an effect on performance penalties, while instead power consumption is lowered by 10 to 20 percent. Changes in voltage and frequency takes place in nanoseconds and is continuously monitored.
Each "Excavator" core has ten so-called Adaptive Voltage Frequency Scaling modules (AVFS), that adjust the voltage and frequency within a core's various components. Further factors, such as temperature and chip quality, also play a role. In addition, there are faster changes between different operating states. The new "Excavator" cores can change from S0i3 power state, in which the core absorbs less than 50 mW, to full load within the space of just a few milliseconds. In addition, parts of the APU will shut down entirely in the Soi3 power state.
New power saving mechanisms such as "Interframe Power Gating" can also be found in the new "Carrizo" APUs. The graphics unit is shut down for as long as the frame buffer is entirely full. Switching off in the space of a few milliseconds already makes it possible to substantially lower power consumption. Overall, AMD states is has pushed idle power from 4,5 watters to 2,7 watts. The highest increases in power efficiency on the APU are mainly thanks to the discontinued Southbridge, as the AMD Fusion Controller Hub (FCH) no longer needs to be manufactured in the 65 and 45 nm process, and instead is now directly on the APU chip itself.
Graphics changed only slightly
On the part of the graphics unit, only a few changes were made to the architecture. However, further optimizations were made to increase its efficiecny. The GFX-L2 cache is now sized 512 KB, a revised ISA instruction set was added and the GCN architecture received a new dot-update and is now on par with "Tonga"m and was optimized for HSA. There is full DirectX12 support, as well as eight more compute cores, which at the same time form the smallest unit.
A Compute Unit consists of four SIMDs with 16 ALUs. In maximum configuration, "Carrizo" provides 512 shader CPUs (8 x 4 CUs SIMDs x 16 ALUs), just like "Kaveri". Since four texture units are connected to each shader cluster, a total of 32 TMUs are available. The memory interface has a width of 128 bits. YThe graphics solutions shares memory with the main memory. The memory controller of "Carrizo" continues to be able to handle 2,133 MHz fast DDR3 memory in dual channel mode. According to AMD, the chip is also designed to already support DDR4, but platform is it not yet designed.
In addition, the new Unified Video Decoder in version 6 is on board, which now copes with HEVC/H.265 and 4K content and is about 3,5 times faster than the previous version. AMD plans on publishing a matching Handbrake tool some time this year, a beta version is currently being tested internally.
Safety is important
As an alternative to Intel's Trusted Execution Technology, AMD integrated its TrustZone tech into "Carrizo", featuring an AMD Secure Processor in the form of an ARM Cortex A5 chip. HSA 1.0 is fully supported. Above all, two functions were repeatedly emphasized: "Shared System Memory" and "Heterogeneous Queuing". The first technology creates memory which can be used by both the CPU as well as the GPU cores, allowing both functional units to be kept up to date and directly interchange their data. This eliminates time consuming copying of data.
This "Huma" shared memory is a prerequisite for hQ. So far, the CPU was considered a master unit and was responsible for the entire program sequence. Now, the GPU can direclty feed the CPU with jobs, meaning both functional units are on equal footing, while handling different tasks. While CPUs are better suited for serial tasks, the strengths of a GPU are parallel computing tasks. AMD AMD promises greater efficiency by distributing task. Expressed in numbers: the new "Steamroller" cores offer up to 20 percent higher performance than the previous generation. AMD sees the future with lots of potential in dividing tasks between the CPU and GPU, as well as outsourcing parallelizable operations into HSA.
The "Carrizo" APU series
The fastest "Carrizo" APUs will have 12 compute cores, consisting of four CPU and eight GPU parts. The new APUs will be placed in the FP4 package, and be able to draw on more than 512 third generation GCN units. A memory controller for DDR3 memory with speeds of up to 2,133 MHz in dual channel mode is also included. As for connections the new APUs will be able to deal with three displays, offer support for True Audio, HSA 1.0 and the security features mentioned above. Should a notebook manufacturer want to use a discrete graphics solution, "Carrizo" offers up to eight PCI Express 3.0 lanes.
Notebook manufacturers will be able to limit power consumption - and thus performance - of the top models in the BIOS, in order to ensure longer battery life. Here, this is similar to the AMD A10-7800. "Carrizo" will be launcehd with a maximum power consumption of 35 watts that goes all the way down to 15 watts. The new APUs will hit the market as AMD FX, A10 and A8 models. AMD has yet to share more information on the individual clock speeds and differences.
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